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features description/ordering information p82b96 dual bidirectional bus buffer scps144b ? may 2006 ? revised july 2007 operating power-supply voltage range forward (tx/ty) and reverse (rx/ry) signals of 2 v to 15 v for interface with optoelectrical isolators and similar devices that need unidirectional can interface between i 2 c buses operating at input and output signal paths different logic levels (2 v to 15 v) 400-khz fast i 2 c bus operation over at least supports bidirectional data transfer of i 2 c 20 meters of wire bus signals low standby current consumption allows bus capacitance of 400 pf on the main i 2 c bus (sx/sy side) and 4000 pf on the latch-up performance exceeds 100 ma per transmission side (tx/ty) jesd 78, class ii outputs on the transmission side (tx/ty) esd protection exceeds jesd 22 have high sink capability for driving ? 3500-v human-body model (a114-a) low-impedance or high-capacitive buses ? 200-v machine model (a115-a) i 2 c bus signals can be split into pairs of ? 1000-v charged-device model (c101) the p82b96 is a bipolar device that supports bidirectional data transfer between the normal i 2 c bus and a range of other bus configurations with different voltage and current levels. it can function as the interface without any limitations on the normal i 2 c operation and clock speed. ordering information t a package (1) (2) orderable part number top-side marking pdip ? p tube of 50 p82b96p p82b96p reel of 2000 p82b96dr soic ? d pg96 tube of 75 p82b96d ?40 c to 85 c reel of 2000 p82b96pwr tssop ? pw pg96 tube of 150 p82b96pw vssop ? dgk reel of 2500 p82b96dgkr 7ds (1) package drawings, thermal data, and symbolization are available at www.ti.com/packaging . (2) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti website at www.ti.com . please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2006?2007, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. d package (top view) gnd 12 3 4 5 6 7 8 sx rx tx ty ry sy v cc p package (top view) 12 3 4 5 6 7 8 sx rx tx gnd ty ry sy v cc dgk package (top view) 12 3 4 5 6 7 8 ty ry sy v cc sx rx tx gnd pw package (top view) 12 3 4 5 6 7 8 sx rx tx gnd ty ry sy v cc www.ti.com
description/ordering information (continued) p82b96 dual bidirectional bus buffer scps144b ? may 2006 ? revised july 2007 one of the advantages of the p82b96 is that it can isolate bus capacitance such that the total loading (devices and trace lengths) of the new bus or remote i 2 c nodes are not apparent to other i 2 c buses (or nodes). this device also adds minimal loading to i 2 c node where it is positioned. any restrictions on the number of i 2 c devices in a system, or the physical separation between them, are virtually eliminated. the p82b96 easily can transmit sda/scl signals via balanced transmission lines (twisted pairs) or with galvanic isolation (optocoupling), because separate directional tx and rx signals are provided. the tx and rx signals may be connected directly (without causing bus latching), to provide an alternative bidirectional signal line with i 2 c properties. two or more sx or sy i/os must not be interconnected. the p82b96 design does not support this configuration. bidirectional i 2 c signals do not allow any direction control pin so, instead, slightly different logic low-voltage levels are used at sx/sy to avoid latching of this buffer. a regular i 2 c low applied at the rx/ry of a p82b96 is propagated to sx/sy as a buffered low with a slightly higher voltage level. if this special buffered low is applied to the sx/sy of another p82b96, the second p82b96 does not recognize it as a regular i 2 c bus low and does not propagate it to its tx/ty output. the sx/sy side of p82b96 may not be connected to similar buffers that rely on special logic thresholds for their operation, such as the pca9515a. the sx/sy side is intended only for, and compatible with, the normal i 2 c logic voltage levels of i 2 c master and slave devices or tx/rx signals of a second p82b96, if required. the tx/rx and ty/ry i/o pins use the standard i 2 c logic voltage levels of all i 2 c parts. if rx and tx are connected, sx can function as either the sda or scl line. similarly, if ry and ty are connected, sy can function as either the sda or scl line. there are no restrictions on the interconnection of the tx/rx and ty/ry i/o pins to other p82b96s, for example in a star or multi-point configuration with the tx/rx and ty/ry i/o pins on the common bus, and the sx/sy side connected to the line-card slave devices. terminal functions no. name description 1 sx serial data bus or sda. connect to v cc of i 2 c master through a pullup resistor. 2 rx receive signal. connect to v cc of p82b96 through a pullup resistor. 3 tx transmit signal. connect to v cc of p82b96 through a pullup resistor. 4 gnd ground 5 ty transmit signal. connect to v cc of p82b96 through a pullup resistor. 6 ry receive signal. connect to v cc of p82b96 through a pullup resistor. 7 sy serial clock bus or scl. connect to v cc of i 2 c master through a pullup resistor. 8 v cc supply voltage 2 submit documentation feedback www.ti.com
functional description sx and sy tx and ty p82b96 dual bidirectional bus buffer scps144b ? may 2006 ? revised july 2007 functional block diagram the i 2 c pins, sx and sy, are designed to interface with a normal i 2 c bus. the logic threshold-voltage levels on the i 2 c bus are independent of the supply v cc . the maximum i 2 c bus supply voltage is 15 v, and the specified static sink current is 3 ma. sx and sy have two identical buffers. each buffer is made up of two logic signal paths. the first one, named tx or ty, is a forward path from the i 2 c interface pin, which drives the buffered bus. the second one, named rx or ry, is a reverse signal path from the buffered bus input to drive the i 2 c bus interface. there are two purposes for these paths: to sense the voltage state of the i 2 c pin (sx or sy) and transmit this state to tx or ty, respectively, and to detect the state of the rx or ry and pull the i 2 c pin low when rx or ry is low. tx and ty are open-collector outputs without esd protection diodes to v cc . each pin may be connected via a pullup resistor to a supply voltage in excess of v cc , as long as the 15-v rating is not exceeded. tx and ty have a larger current-sinking capability than a normal i 2 c device and can sink a static current of greater than 30 ma. they also have dynamic pulldown capability of 100-ma, typically. a logic low is transmitted to tx or ty only when the voltage at the i 2 c pin (sx or sy) is below 0.6 v. a logic low at rx or ry causes the i 2 c bus (sx or sy) to be pulled to a logic low level in accordance with i 2 c requirements (maximum 1.5 v in 5-v applications), but not low enough to be looped back to the tx or ty output and cause the buffer to latch low. the minimum low level that the p82b96 can achieve on the i 2 c bus by a low at rx or ry typically is 0.8 v. if v cc fails, neither the i 2 c pins nor the tx or ty outputs are held low. their open-collector configuration allows them to be pulled up to the rated maximum of 15 v without v cc present. the input configuration on sx, sy, rx, and ry also presents no loading of external signals when v cc is not present. the effective input capacitance of any signal pin, measured by its effect on bus rise times, is less than 4 pf for all bus voltages and supply voltages, including v cc = 0 v. 3 submit documentation feedback p82b96 sx (sda) sy (scl) ry (rxd, scl) ty (txd, scl) rx (rxd, sda) tx (txd, sda) 17 4 gnd 6 5 2 3 8 v (2C15 v) cc www.ti.com
absolute maximum ratings (1) recommended operating conditions p82b96 dual bidirectional bus buffer scps144b ? may 2006 ? revised july 2007 over operating free-air temperature range (unless otherwise noted) min max unit v cc supply voltage range ?0.3 18 v sx or sy (sda or scl) ?0.3 18 v i voltage range on buffered input v rx or ry ?0.3 18 sx or sy (sda or scl) ?0.3 18 v o voltage range on buffered output v tx or ty ?0.3 18 sx or sy 250 i o continuous output current ma tx or ty 250 i cc continuous current through v cc or gnd 250 ma d package 97 p package 85 ja package thermal impedance (2) c/w pw package 149 dgk package 172 t stg storage temperature range ?55 125 c t a operating free-air temperature range ?40 85 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the package thermal impedance is calculated in accordance with jesd 51-7. min max unit v cc supply voltage 2 15 v sx, sy v sx , v sy = 1 v, v rx , v ry 0.42 v 3 i ol low-level output current ma tx, ty v sx , v sy = 0.4 v, v tx , v ty = 0.4 v 30 sx, sy v tx , v ty = 0.4 v 15 v iomax maximum input/output voltage level v tx, ty v sx , v sy = 0.4 v 15 v ildiff low-level input voltage difference sx, sy 0.4 v t a operating free-air temperature ?40 85 c 4 submit documentation feedback www.ti.com
electrical characteristics p82b96 dual bidirectional bus buffer scps144b ? may 2006 ? revised july 2007 v cc = 2.3 v to 2.7 v, voltages are specified with respect to gnd (unless otherwise noted) t a = 25 c t a = ?40 c to 85 c test parameter unit conditions min typ (1) max min max temperature coefficient of v/ t in sx, sy ?2 mv/ c input thresholds i sx , i sy = 3 ma 0.8 0.88 1 v ol low-level output voltage sx, sy (2) v i sx , i sy = 0.2 ma 0.67 0.73 0.79 (2) temperature coefficient of v/ t out sx, sy i sx , i sy = 0.2 ma ?1.8 mv/ c output low levels (3) i cc quiescent supply current sx = sy = v cc 0.9 1.8 2 ma additional supply current i cc tx, ty 1.7 2.75 3 ma per pin low dynamic output sink v sx , v sy > 2 v, 7 18 5.5 ma capability on i 2 c bus v rx , v ry = low i ios sx, sy v sx , v sy = 2.5 v, leakage current on i 2 c bus 0.1 1 1 a v rx , v ry = high v tx , v ty > 1 v, dynamic output sink tx, ty v sx , v sy = low on 60 100 60 ma capability on buffered bus i 2 c bus = 0.4 v i iot v tx , v ty = v cc = leakage current 2.5 v, 0.1 1 1 a on buffered bus v sx , v sy = high bus low, v rx , input current from i 2 c bus sx, sy ?1 1 v ry = high input current bus low, v rx , i i ?1 1 a from buffered bus v ry = 0.4 v rx, ry leakage current v rx , v ry = v cc 1 1.5 on buffered bus input input logic level high threshold (4) 0.65 0.7 (2) on normal i 2 c bus sx, sy input logic level low threshold (4) 0.6 0.65 (2) v it input threshold v on normal i 2 c bus input logic level high 0.58 v cc 0.58 v cc rx, ry input threshold 0.5 v cc input logic level low 0.42 v cc 0.42 v cc (v sx output low input/output logic level at 3 ma) ? v iodiff sx, sy 100 150 100 mv difference (5) (v sx input high max) for i 2 c applications sx, sy are low, v cc v cc voltage at which all sx, sy ramping, voltage on v iorel 1 1 v buses are released tx, ty tx, ty lowered until released temperature coefficient of release v/ t rel ?4 mv/ c voltage c in input capacitance rx, ry 2.5 4 4 pf (1) typical value is at v cc = 2.5 v, t a = 25 c (2) see the typical characteristics section of this data sheet. (3) the output logic low depends on the sink current. (4) the input logic threshold is independent of the supply voltage. (5) the minimum value requirement for pullup current, 200 a, ensures that the minimum value for v sx output low always exceeds the minimum v sx input high level to eliminate any possibility of latching. the specified difference is specified by design within any device. while the tolerances on absolute levels allow a small probability that the low from one sx output is recognized by an sx input of another p82b96, this has no consequences for normal applications. in any design, the sx pins of different devices should never be linked, because the resulting system would be very susceptible to induced noise and would not support all i 2 c operating modes. 5 submit documentation feedback www.ti.com
electrical characteristics p82b96 dual bidirectional bus buffer scps144b ? may 2006 ? revised july 2007 v cc = 3 v to 3.6 v, voltages are specified with respect to gnd (unless otherwise noted) t a = 25 c t a = ?40 c to 85 c parameter test conditions unit min typ (1) max min max temperature v/ t in coefficient of sx, sy ?2 mv/ c input thresholds i sx , i sy = 3 ma 0.8 0.88 1 low-level output v ol sx, sy (2) v voltage i sx , i sy = 0.2 ma 0.67 0.73 0.79 (2) temperature coefficient of v/ t out sx, sy i sx , i sy = 0.2 ma ?1.8 mv/ c output low levels (3) i cc quiescent supply current sx = sy = v cc 0.9 1.8 2 ma additional supply i cc current per pin tx, ty 1.7 2.75 3 ma low dynamic output v sx , v sy > 2 v, sink capability 7 18 5.7 ma v rx , v ry = low on i 2 c bus i ios sx, sy leakage current v sx , v sy = 5 v, 0.1 1 1 a on i 2 c bus v rx , v ry = high dynamic output v tx , v ty > 1 v, sink capability v sx , v sy = low on i 2 c 60 100 60 ma on buffered bus bus = 0.4 v i iot tx, ty leakage current v tx , v ty = v cc = 0.1 1 1 a on buffered bus 3.3 v, v sx , v sy = high input current bus low, v rx , sx, sy ?1 1 from i 2 c bus v ry = high input current bus low, v rx , ?1 1 i i from buffered bus v ry = 0.4 v a rx, ry leakage current on buffered bus v rx , v ry = v cc 1 1.5 input input logic-level high threshold (4) 0.65 0.7 (2) on normal i 2 c bus sx, sy input logic-level low threshold (4) 0.6 0.65 (2) v it input threshold v on normal i 2 c bus input logic level high 0.58 v cc 0.58 v cc rx, ry input threshold 0.5 v cc input logic level low 0.42 v cc 0.42 v cc (v sx output low input/output logic at 3 ma) ? v iodiff sx, sy 100 150 100 mv level difference (5) (v sx input high max) for i 2 c applications sx, sy are low, v cc v cc voltage at sx, sy ramping, voltage on v iorel which all buses 1 1 v tx, ty tx, ty lowered until are released released (1) typical value is at v cc = 3.3 v, t a = 25 c (2) see the typical characteristics section of this data sheet. (3) the output logic low depends on the sink current. (4) the input logic threshold is independent of the supply voltage. (5) the minimum value requirement for pullup current, 200 a, ensures that the minimum value for v sx output low always exceeds the minimum v sx input high level to eliminate any possibility of latching. the specified difference is specified by design within any device. while the tolerances on absolute levels allow a small probability that the low from one sx output is recognized by an sx input of another p82b96, this has no consequences for normal applications. in any design, the sx pins of different devices never should be linked, because the resulting system would be very susceptible to induced noise and would not support all i 2 c operating modes. 6 submit documentation feedback www.ti.com
p82b96 dual bidirectional bus buffer scps144b ? may 2006 ? revised july 2007 electrical characteristics (continued) v cc = 3 v to 3.6 v, voltages are specified with respect to gnd (unless otherwise noted) t a = 25 c t a = ?40 c to 85 c parameter test conditions unit min typ (1) max min max temperature coefficient of v/ t rel ?4 mv/ c release voltage c in input capacitance rx, ry 2.5 4 4 pf 7 submit documentation feedback www.ti.com
electrical characteristics p82b96 dual bidirectional bus buffer scps144b ? may 2006 ? revised july 2007 v cc = 4.5 v to 5.5 v, voltages are specified with respect to gnd (unless otherwise noted) t a = 25 c t a = ?40 c to 85 c parameter test conditions unit min typ (1) max min max temperature v/ t in coefficient of sx, sy ?2 mv/ c input thresholds i sx , i sy = 3 ma 0.8 0.88 1 low-level output v ol sx, sy (2) v voltage i sx , i sy = 0.2 ma 0.67 0.73 0.79 (2) temperature coefficient of v/ t out sx, sy i sx , i sy = 0.2 ma ?1.8 mv/ c output low levels (3) i cc quiescent supply current sx = sy = v cc 0.9 1.8 2 ma additional supply i cc current tx, ty 1.7 2.75 3 ma per pin low dynamic output v sx , v sy > 2 v, sink capability 7 18 6 ma v rx , v ry = low on i 2 c bus i ios sx, sy leakage current v sx , v sy = 5 v, 0.1 1 1 a on i 2 c bus v rx , v ry = high dynamic output v tx , v ty > 1 v, sink capability v sx , v sy = low on 60 100 60 ma on buffered bus i 2 c bus = 0.4 v i iot tx, ty leakage current v tx , v ty = v cc = 0.1 1 1 a on buffered bus 5 v, v sx , v sy = high input current bus low, v rx , sx, sy ?1 1 from i 2 c bus v ry = high input current bus low, v rx , ?1 1 i i from buffered bus v ry = 0.4 v a rx, ry leakage current on buffered bus v rx , v ry = v cc 1 1.5 input input logic-level high threshold (4) 0.65 0.7 (2) on normal i 2 c bus sx, sy input logic-level low threshold (4) 0.6 0.65 (2) v it input threshold v on normal i 2 c bus input logic level high 0.58 v cc 0.58 v cc rx, ry input threshold 0.5 v cc input logic level low 0.42 v cc 0.42 v cc (v sx output low at input/output logic 3 ma) ? v iodiff sx, sy 100 150 100 mv level difference (5) (v sx input high max) for i 2 c applications sx, sy are low, v cc v cc voltage at sx, sy ramping, voltage on v iorel which all buses 1 1 v tx, ty tx, ty lowered until are released released (1) typical value is at v cc = 5 v, t a = 25 c (2) see the typical characteristics section of this data sheet. (3) the output logic low depends on the sink current. (4) the input logic threshold is independent of the supply voltage. (5) the minimum value requirement for pullup current, 200 a, ensures that the minimum value for v sx output low always exceeds the minimum v sx input high level to eliminate any possibility of latching. the specified difference is specified by design within any device. while the tolerances on absolute levels allow a small probability that the low from one sx output is recognized by an sx input of another p82b96, this has no consequences for normal applications. in any design, the sx pins of different devices never should be linked, because the resulting system would be very susceptible to induced noise and would not support all i 2 c operating modes. 8 submit documentation feedback www.ti.com
p82b96 dual bidirectional bus buffer scps144b ? may 2006 ? revised july 2007 electrical characteristics (continued) v cc = 4.5 v to 5.5 v, voltages are specified with respect to gnd (unless otherwise noted) t a = 25 c t a = ?40 c to 85 c parameter test conditions unit min typ (1) max min max temperature coefficient of v/ t rel ?4 mv/ c release voltage c in input capacitance rx, ry 2.5 4 4 pf 9 submit documentation feedback www.ti.com
electrical characteristics p82b96 dual bidirectional bus buffer scps144b ? may 2006 ? revised july 2007 v cc = 15 v, voltages are specified with respect to gnd (unless otherwise noted) t a = 25 c t a = ?40 c to 85 c parameter test conditions unit min typ (1) max min max temperature v/ t in coefficient of sx, sy ?2 mv/ c input thresholds i sx , i sy = 3 ma 0.8 0.88 1 low-level output v ol sx, sy (2) v voltage i sx , i sy = 0.2 ma 0.67 0.73 0.79 (2) temperature coefficient of v/ t out sx, sy i sx , i sy = 0.2 ma ?1.8 mv/ c output low levels (3) quiescent supply i cc sx = sy = v cc 0.9 1.8 2 ma current additional supply i cc current tx, ty 1.7 2.75 3 ma per pin low dynamic output v sx , v sy > 2 v, sink capability 7 18 6.5 ma v rx , v ry = low on i 2 c bus i ios sx, sy leakage current v sx , v sy = 15 v, 0.1 1 1 a on i 2 c bus v rx , v ry = high dynamic output v tx , v ty > 1 v, sink capability v sx , v sy = low on 60 100 60 ma on buffered bus i 2 c bus = 0.4 v i iot tx, ty v tx , v ty = v cc = leakage current 15 v, 0.1 1 1 a on buffered bus v sx , v sy = high input current bus low, v rx , sx, sy ?1 1 from i 2 c bus v ry = high input current bus low, v rx , ?1 1 i i from buffered bus v ry = 0.4 v a rx, ry leakage current on buffered bus v rx , v ry = v cc 1 1.5 input input logic-level high threshold (4) 0.65 0.7 (2) on normal i 2 c bus sx, sy input logic-level high threshold (4) 0.6 0.65 (2) v it input threshold v on normal i 2 c bus input logic level high 0.58 v cc 0.58 v cc rx, ry input threshold 0.5 v cc input logic level low 0.42 v cc 0.42 v cc (v sx output low at input/output logic 3 ma) ? v iodiff sx, sy 100 150 100 mv level difference (5) (v sx input high max) for i 2 c applications (1) typical value is at v cc = 15 v, t a = 25 c (2) see the typical characteristics section of this data sheet. (3) the output logic low depends on the sink current. (4) the input logic threshold is independent of the supply voltage. (5) the minimum value requirement for pullup current, 200 a, ensures that the minimum value for v sx output low always exceeds the minimum v sx input high level to eliminate any possibility of latching. the specified difference is specified by design within any device. while the tolerances on absolute levels allow a small probability that the low from one sx output is recognized by an sx input of another p82b96, this has no consequences for normal applications. in any design, the sx pins of different devices never should be linked, because the resulting system would be very susceptible to induced noise and would not support all i 2 c operating modes. 10 submit documentation feedback www.ti.com
switching characteristics p82b96 dual bidirectional bus buffer scps144b ? may 2006 ? revised july 2007 electrical characteristics (continued) v cc = 15 v, voltages are specified with respect to gnd (unless otherwise noted) t a = 25 c t a = ?40 c to 85 c parameter test conditions unit min typ (1) max min max sx, sy are low, v cc v cc voltage at sx, sy ramping, voltage on v iorel which all buses 1 1 v tx, ty tx, ty lowered until are released released temperature coefficient of v/ t rel ?4 mv/ c release voltage c in input capacitance rx, ry 2.5 4 4 pf v cc = 5 v, t a = 25 c, no capacitive loads, voltages are specified with respect to gnd (unless otherwise noted) from to parameter test conditions typ unit (input) (output) r tx pullup = 160 w , buffer delay time on falling v sx (or v sy ) = input switching v tx (or v ty ) output falling t pzl c tx = 7 pf + board 70 ns input (1) threshold 50% of v load trace capacitance r tx pullup = 160 w , buffer delay time on rising v sx (or v sy ) = input switching v tx (or v ty ) output t plz c tx = 7 pf + board 90 ns input (2) threshold reaching 50% of v load trace capacitance r sx pullup = 1500 w , buffer delay time on falling v rx (or v ry ) = input switching v sx (or v sy ) output falling t pzl c tx = 7 pf + board 250 ns input (3) threshold 50% of v load trace capacitance r sx pullup = 1500 w , buffer delay time on rising v rx (or v ry ) = input switching v sx (or v sy ) output t plz c tx = 7 pf + board 270 ns input (4) threshold reaching 50% of v load trace capacitance (1) the fall time of v tx from 5 v to 2.5 v in the test is approximately 15 ns. (2) the fall time of v sx from 5 v to 2.5 v in the test is approximately 50 ns. (3) the rise time of v tx from 0 v to 2.5 v in the test is approximately 20 ns. (4) the rise time of v sx from 0.9 v to 2.5 v in the test is approximately 70 ns. 11 submit documentation feedback www.ti.com
typical characteristics p82b96 dual bidirectional bus buffer scps144b ? may 2006 ? revised july 2007 v ol at sx v ol at sx vs vs junction temperature junction temperature i ol = 0.2 ma i ol = 3 ma v il(max) at sx v ih(min) at sx vs vs junction temperature junction temperature v cc(max) vs junction temperature 12 submit documentation feedback 1000 200 800600 400 -50 100 75 50 25 0 ?25 125 v ? mv il(max) t ? c j 600 800 1000 400 -50 100 75 50 25 0 ?25 125 v ? mv ol t ? c j maximum typical minimum 600 1400 400 800 1000 1200 -50 100 75 50 25 0 ?25 125 v ? mv cc(max) t ? c j 1000 200 800600 400 -50 100 75 50 25 0 ?25 125 v ? mv ih(min) t ? c j www.ti.com 1200 400 1000 800600 -50 100 75 50 25 0 ?25 125 v ? mv ol t ? c j maximum typical minimum
parameter measurement information p82b96 dual bidirectional bus buffer scps144b ? may 2006 ? revised july 2007 a. c l includes probe and jig capacitance. b. all inputs are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r /t f 30 ns. figure 1. test circuit and voltage waveforms 13 submit documentation feedback t plz /t pzl v cc test s1 c = probe and jig capacitance (see note a) l s1 gnd r = 160 to 1500 l w v cc tx or ty pulse generator dut r t v cc v in v out t plz t pzl v cc 0 v sx or sy voltage waveforms propagation delay and output transition times test circuit for open-drain output 0.6 v v cc v ol 0.5 v cc www.ti.com
application information typical applications p82b96 dual bidirectional bus buffer scps144b ? may 2006 ? revised july 2007 figure 2 through figure 4 show typical applications for the p82b96. figure 2. interfacing i 2 c bus with different logic levels figure 3. galvanic isolation of i 2 c nodes figure 4. long-distance i 2 c communications 14 submit documentation feedback 5 v v (2C15v) cc r1 1/2 pb2b96 tx(sda) rx (sda) sda(new levels) i c sda 2 scl scl sda p82b96 main enclosure remote-control enclosure 3.3C5 v 3.3C5 v 12 v 12 v 12 v long cables 3.3C5 v 3.3C5 v sda p82b96 5 v 1/2 p82b96 i c 2 sda r1 tx (sda) rx (sda) r2 r3 v cc v cc1 r4 r5 i c 2 sda www.ti.com
p82b96 dual bidirectional bus buffer scps144b ? may 2006 ? revised july 2007 application information (continued) figure 5 shows how a master i 2 c bus can be protected against short circuits or failures in applications that involve plug/socket connections and long cables that may become damaged. a simple circuit is added to monitor the sda bus and, if its low time exceeds the design value, disconnect the master bus. p82b96 frees all of its i/os if its supply is removed, so one option is to connect its v cc to the output of a logic gate from, for example, the lvc family. the sda and scl lines could be timed, and v cc disabled via the gate, if a line exceeds a design value of the low period. if the supply voltage of logic gates restricts the choice of v cc supply, the low-cost discrete circuit in figure 5 can be used. if the sda line is held low, the 100-nf capacitor charges, and ry is pulled toward v cc . when it exceeds v cc /2, ry sets sy high, which effectively releases it. figure 5. extending dcc bus in this example, the scl line is made unidirectional by tying rx to v cc . the state of the buffered scl line cannot affect the master clock line, which is allowed when clock stretching is not required. it is simple to add an additional transistor or diode to control the rx input in the same way as ry, when necessary. the +v cable drive can be any voltage up to 15 v, and the bus may be run at a lower impedance by selecting pullup resistors for a static sink current up to 30 ma. v cc1 and v cc2 may be chosen to suit the connected devices. because ddc uses relatively low speeds (<100 khz), the cable length is not restricted to 20 m by the i 2 c signaling, but it may be limited by the video signaling. figure 6 and table 1 show that p82b96 can achieve high clock rates over long cables. while calculating with lumped wiring capacitance yields reasonable approximations to actual timing; even 25 m of cable is better treated using transmission line theory. flat ribbon cables connected as shown, with the bus signals on the outer edge, have a characteristic impedance in the range 100?200 w . for simplicity, they cannot be terminated in their characteristic impedance, but a practical compromise is to use the minimum pullup allowed for p82b96 and place half this termination at each end of the cable. when each pullup is below 330 w , the rising-edge waveforms have their first voltage step level above the logic threshold at rx, and cable timing calculations can be based on the fast rise/fall times of resistive loading, plus simple one-way propagation delays. when the pullup is larger, but below 750 w , the threshold at rx is crossed after one signal reflection. so, at the sending 15 submit documentation feedback scl scl sda p82b96 3-m to 20-m cables p82b96 v +v cable drive v cc i c/ddc 2 master gnd sx sy rxtx ry ty 470 k w 4700 w i c/ddc 2 rx tx ty ry v cc1 v cc2 sx sy i c/ddc 2 slave pc/tv receiver/decoder box monitor/flat tv video signals rg b 100 k w 100 nf 470 k w +v cable drive v cc gnd bc847b bc847b sda www.ti.com
p82b96 dual bidirectional bus buffer scps144b ? may 2006 ? revised july 2007 application information (continued) end, it is crossed after two times the one-way propagation delay and, at the receiving end, after three times that propagation delay. for flat cables with partial plastic dielectric insulation (by using outer cores) the one-way propagation delays are about 5 ns/m. the 10% to 90% rise and fall times on the cable are between 20 ns and 50 ns, so their delay contributions are small. there is ringing on falling edges that can be damped, if required, using schottky diodes, as shown. figure 6. driving ribbon or flat telephone cables table 1. bus capabilities master scl bus maximum pulse +v cable cable v cc1 v cc2 r1 r2 c2 cable clock slave duration cable length delay (v) (v) ( w ) (k w ) (pf) capacitance speed response (ns) (v) (m) (ns) (khz) delay high low 5 12 5 750 2.2 400 250 (1) 1250 600 4000 120 (2) 5 12 5 750 2.2 220 100 (1) 500 600 2600 185 (2) 3.3 5 3.3 330 1 220 25 1 nf 125 600 1500 390 (2) 3.3 5 3.3 330 1 100 3 120 pf 15 600 1000 500 600 ns (1) not applicable; calculations are delay based. (2) normal 400-khz bus specification when the master scl high and low periods can be programmed separately, the timings can allow for bus delays. the low period should be programmed to achieve the minimum 1300 ns plus the net delay in the slave response data signal caused by bus and buffer delays. the longest data delay is the sum of the delay of the falling edge of scl from master to slave and the delay of the rising edge of sda from slave data to master. because the buffer stretches the programmed scl low period, the actual scl frequency is lower than calculated from the programmed clock periods. in the example for the 25-m cable in table 1 , the clock is stretched 400 ns, the falling edge of scl is delayed 490 ns, and the sda rising edge is delayed 570 ns. the required additional low period is (490 + 570) = 1060 ns and the i 2 c bus specifications already include an allowance for a worst-case bus rise time (0% to 70%) of 425 ns. the bus rise time can be 300 ns (30% to 70%), which means it can be 425 ns (0% to 70%). the 25-m cable delay times include all rise and fall times. therefore, the device only needs to be programmed with an additional (1060 ? 400 ? 425) = 235 ns, making a total programmed low period 1535 ns. the programmed low is stretched by 400 ns to yield an actual bus low time of 1935 ns, which, allowing the minimum high period of 600 ns, yields a cycle period of 2535 ns or 394 khz. 16 submit documentation feedback sclsda p82b96 gnd scl sda p82b96 r1 r1 r2 r2 r2 r2 r1 r1 cable +v cable drive propagation delay = 5 ns/m i c master 2 i c slave(s) 2 c2 c2 v cc1 v cc rxtx ry ty sx sy v cc rxtx ry ty sx sy v cc2 gnd bat54a bat54a c2 c2 www.ti.com
calculating system delays and bus-clock frequency for fast mode system p82b96 dual bidirectional bus buffer scps144b ? may 2006 ? revised july 2007 note that, in both the 100-m and 250-m examples, the capacitive loading on the i 2 c buses at each end is within the maximum allowed standard mode loading of 400 pf, but exceeds the fast mode limit. this is an example of a hybrid mode, because it relies on the response delays of fast mode parts, but uses (allowable) standard mode bus loadings with rise times that contribute significantly to the system delays. the cables cause large propagation delays. therefore, these systems must operate well below the 400-khz limit, but illustrate how they still can exceed the 100-khz limit, provided all parts are capable of fast mode operation. the fastest example illustrates how the 400-khz limit can be exceeded, provided master and slave parts have delay specifications smaller than the maximum allowed. many ti slaves have delays shorter than 600 ns, but none have that specified. figure 7 through figure 9 show the p82b96 used to drive extended bus wiring, with relatively large capacitance, linking two fast mode i 2 c bus nodes. it includes simplified expressions for making the relevant timing calculations for 3.3-/5-v operation. because the buffers and the wiring introduce timing delays, it may be necessary to decrease the nominal scl frequency below 400 khz. in most cases, the actual bus frequency is lower than the nominal master timing, due to bit-wise stretching of the clock periods. figure 7. figure 8. 17 submit documentation feedback master p82b96 v ccm scl rm rb sx tx/rx tx/rx gnd v ccb i c 2 cb = buffered bus wiring capacitance cm = master buscapacitance rising edge of scl at master is delayed (clock stretch) by buffer and bus rise times. effective delay of scl at master = 270 + rmcm + 0.7rbcb (ns) c = f, r = local master bus buffered expansion bus www.ti.com master i c 2 i c 2 slave p82b96 p82b96 scl rm rb rs v ccs scl sx tx/rx tx/rx sx gnd falling edge of scl at master is delayed by the buffers and bus fall times. local master bus v ccb effective delay of scl at slave = 255 + 17 v + (2.5 + 4 10 cb) v (ns) c = f, v = volts ccm ccb 9 v ccm cb = buffered bus wiring capacitance cm = master buscapacitance cs = slave buscapacitance buffered expansion bus remote slave bus
p82b96 dual bidirectional bus buffer scps144b ? may 2006 ? revised july 2007 figure 9. the delay factors involved in calculation of the allowed bus speed are: 1. the propagation delay of the master signal through the buffers and wiring to the slave. the important delay is that of the falling edge of scl, because this edge requests the data or ack from a slave. 2. the effective stretching of the nominal low period of scl at the master, caused by the buffer and bus rise times. 3. the propagation delay of the slave response signal through the buffers and wiring back to the master. the important delay is that of a rising edge in the sda signal. rising edges always are slower and, therefore, are delayed by a longer time than falling edges. (the rising edges are limited by the passive pullup, while falling edges actively are driven.) the timing requirement in any i 2 c system is that a slave?s data response (which is provided in response to a falling edge of scl) must be received at the master before the end of the corresponding low period of scl as it appears on the bus wiring at the master. because all slaves, as a minimum, satisfy the worst-case timing requirements of a 400-khz part, they must provide their response within the minimum allowed clock low period of 1300 ns. therefore, in systems that introduce additional delays, it is necessary only to extend that minimum clock low period by any effective delay of the slave response. the effective delay of the slave's response equals the total delays in scl falling edge from the master reaching the slave (a) minus the effective delay (stretch) of the scl rising edge (b) plus total delays in the slave response data, carried on sda, and reaching the master (c). the master microcontroller should be programmed to produce a nominal scl low period of (1300 + a ? b + c) ns and should be programmed to produce the nominal minimum scl high period of 600 ns. then, a check should be made to ensure the cycle time is not shorter than the minimum 2500 ns. if found to be necessary, increase either clock period. due to clock stretching, the scl cycle time always is longer than (600 + 1300 + a + c) ns. 18 submit documentation feedback master p82b96 p82b96 sda rm rb rs sda sx tx/rx tx/rx sx gnd i c 2 v ccs local master bus v ccm cb = buffered bus wiring capacitance cm = master buscapacitance cs = slave buscapacitance buffered expansion bus remote slave bus i c 2 slave v ccb rising edge of sda at slave is delayed by the buffers and bus rise times. effective delay of sda at master = 270 + 0.2rscs + 0.7(rbcb + rmcm) (ns) c = f, r = www.ti.com
sample calculations p82b96 dual bidirectional bus buffer scps144b ? may 2006 ? revised july 2007 the master bus has an rmcm product of 100 ns and v ccm = 5 v. the buffered bus has a capacitance of 1 nf and a pullup resistor of 160 w to 5 v, giving an rbcb product of 160 ns. the slave bus also has an rscs product of 100 ns. the master low period should be programmed to be 3 (1300 + 372.5 ? 482 + 472) ns, which calculates to 3 1662.5 ns. the master high period may be programmed to the minimum 600 ns. the nominal master clock period is 3 (1662.5 + 600) ns = 2262.5 ns, equivalent to a frequency of 442 khz. the actual bus-clock period, including the 482-ns clock stretch effect, is below (nominal + stretch) = (2262.5 + 482) ns or 3 2745 ns, equivalent to an allowable frequency of 364 khz. 19 submit documentation feedback www.ti.com
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) p82b96d active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim p82b96dg4 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim p82b96dgkr active msop dgk 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim p82b96dgkrg4 active msop dgk 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim p82b96dr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim p82b96drg4 active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim p82b96p active pdip p 8 50 pb-free (rohs) cu nipdau n / a for pkg type p82b96pe4 active pdip p 8 50 pb-free (rohs) cu nipdau n / a for pkg type p82b96pw active tssop pw 8 150 green (rohs & no sb/br) cu nipdau level-1-260c-unlim P82B96PWG4 active tssop pw 8 150 green (rohs & no sb/br) cu nipdau level-1-260c-unlim p82b96pwr active tssop pw 8 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim p82b96pwrg4 active tssop pw 8 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. package option addendum www.ti.com 25-jul-2007 addendum-page 1
in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 25-jul-2007 addendum-page 2
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant p82b96dgkr msop dgk 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 p82b96dr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 p82b96pwr tssop pw 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 q1 package materials information www.ti.com 17-apr-2009 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) p82b96dgkr msop dgk 8 2500 358.0 335.0 35.0 p82b96dr soic d 8 2500 346.0 346.0 29.0 p82b96pwr tssop pw 8 2000 346.0 346.0 29.0 package materials information www.ti.com 17-apr-2009 pack materials-page 2

mechanical data mtss001c january 1995 revised february 1999 post office box 655303 ? dallas, texas 75265 pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. ti products are not authorized for use in safety-critical applications (such as life support) where a failure of the ti product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of ti products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by ti. further, buyers must fully indemnify ti and its representatives against any damages arising out of the use of ti products in such safety-critical applications. ti products are neither designed nor intended for use in military/aerospace applications or environments unless the ti products are specifically designated by ti as military-grade or "enhanced plastic." only products designated by ti as military-grade meet military specifications. buyers acknowledge and agree that any such use of ti products which ti has not designated as military-grade is solely at the buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti products are neither designed nor intended for use in automotive applications or environments unless the specific ti products are designated by ti as compliant with iso/ts 16949 requirements. buyers acknowledge and agree that, if they use any non-designated products in automotive applications, ti will not be responsible for any failure to meet such requirements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dlp? products www.dlp.com communications and www.ti.com/communications telecom dsp dsp.ti.com computers and www.ti.com/computers peripherals clocks and timers www.ti.com/clocks consumer electronics www.ti.com/consumer-apps interface interface.ti.com energy www.ti.com/energy logic logic.ti.com industrial www.ti.com/industrial power mgmt power.ti.com medical www.ti.com/medical microcontrollers microcontroller.ti.com security www.ti.com/security rfid www.ti-rfid.com space, avionics & www.ti.com/space-avionics-defense defense rf/if and zigbee? solutions www.ti.com/lprf video and imaging www.ti.com/video wireless www.ti.com/wireless-apps mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2010, texas instruments incorporated

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